1. Technical Field
The present invention relates in general to Input/Output (I/O) bus architectures and, in particular, to bus bridges that provide a data interface allowing independent buses to communicate with each other. Specifically, the present invention relates to a transaction tracing circuit embedded in a bus bridge that provides transaction tracing capabilities and a method thereof.
2. Description of the Related Art
With the ever-increasing advances in technology, the number, types and functional power of computer system components has also steadily increased. In computer systems, electronic devices that comprise the computer system are interconnected with one another utilizing buses that provide the means through which the devices can communicate with each other. With the large number and different operating speeds of different components, current computer systems typically include two and possibly more buses for interconnecting the various electronic devices.
Buses are generally classified as central processing unit (CPU) system buses or input/output (I/O) buses. Host buses are typically short in length, capable of transferring data at high speeds, and are matched to a memory system to maximize memory-CPU bandwidth. A designer of a system bus is usually familiar with the types of devices that are to be connected to the host bus and is able to design an efficient system bus to accommodate the needs of the devices. I/O buses, in contrast, are often lengthy and may have a wide variety of disparate devices connected to them. I/O buses also generally have a wide range in the data bandwidth of the devices connected to them.
One device commonly utilized to couple together two different buses is referred to as a bridge chip, also known as a bus bridge. The bus bridge is an electronic device that provides a data interface between independent buses, sometimes operating at different speeds. The bus bridge allows for devices connected to the different buses to communicate with each other. Typically, requests transferred between buses via a bus bridge can be either posted or non-posted. A posted request refers to a request from a source agent on a source bus that has been accepted by the bus bridge. The source agent also knows that the request will be provided to a target agent on the target bus, regardless of whether the request has been actually delivered to the target agent or whether the request is pending in a buffer in the bus bridge. A non-posted request that is being transferred through the bus bridge and the source agent does not know whether the request can be delivered to the target agent until it has been actually received by the target agent.
Monitoring and tracing bus transaction activity, such as the above discussed requests, on a bus bridge is an important tool for determining system performance and trouble-shooting the system. Transaction tracing, such as dynamic usage of instruction types and other fields, address translation and memory reference patterns, provide insight on the behavior of the particular combination of architecture, implementation, system software and application program from which the transaction trace was collected, and so can be used to guide design decisions by system developers. Generally, there are two main components to the process of generating a bus transaction trace: bus capture and trace generation. A system program establishes the state of the system under test by a combination of writing out register values or invalidating caches. This may result in a bus controller starting a transaction by placing a particular address on a bus. An external bus analyzer, such as a logic analyzer, records the bus transaction activity and from this a file of bus transactions is produced. Trace generation proceeds by driving a system simulator with the recorded bus transactions and recoding the sequence that results. A problem inherent with this approach, or in the case of troubleshooting a system problem, is that external devices, i.e., logic analyzers, must be employed to record the transaction trace. In embedded systems this can be of particular concern, since space for debug connectors is usually constrained.
Accordingly, what is needed in the art is an improved bus bridge that does not require the use of external devices to trace bus transactions occurring on the bus bridge. More particularly, what is needed in the art is a bus bridge with embedded transaction tracing capabilities.
It is therefore an object of the invention to provide an improved bus bridge with embedded transaction tracing capabilities.
It is an object of the present invention to provide a transaction tracing circuit for tracing bus transactions that occur on buses connected to the bus bridge, regardless of whether or not the bus bridge is the target of the transaction, i.e. transaction tracing as either the master, slave, or third party to a transaction.
To achieve the foregoing objects, and in accordance with the invention as embodied and broadly described herein a transaction tracing circuit for use with a bus bridge that is couplable to at least a first and a second bus is disclosed. The transaction tracing circuit includes at least one set of trace control registers that is associated with a transaction tracing function for tracing a specific transaction occurring on the bus bridge. A number of bus transaction tracing circuits, one for each bus to which the bridge is connected, are coupled to the trace control registers and are utilized to store transactions that are captured as they occur on the individual buses. An internal transaction tracing circuit is coupled to the trace control registers and is utilized for storing captured internal transaction information corresponding to the specific internal transaction. In a related embodiment, the transaction tracing circuit also includes a correlation circuit, an address control logic and a memory controller. The correlation circuit is coupled to the internal transaction tracing circuit and the bus transaction tracing circuits for correlating the incoming trace requests and prioritizing the storage of information corresponding to the captured bus transaction information. The address control logic is coupled to the trace control register and the correlation circuit for associating the captured bus transaction information that is to be stored with the proper storage control information contained in the trace control registers. The memory controller is coupled to the address control logic and the correlation circuit and performs the store operation to a specified address and routing data to a storage device. In an advantageous embodiment, the memory device is a static random access memory (SRAM) device.
In another embodiment of the present invention, the transaction tracing circuit further includes a checkpoint logic that is coupled to the trace control register for determining address matching and bus command matching when the bus transaction tracing function includes checkpoint tracing. This allows for transaction tracing that is targeted to a specific address, or set of addresses, and bus command type.
The foregoing description has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject matter of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.